The present invention relates generally to manufacturing semiconductor devices, particularly highly miniaturized semiconductor devices having ultra-shallow junction depths. The present invention is particularly applicable to manufacturing highly reliable SOI MOSFETS.
Semiconductor manufacturing techniques undergo constant challenges as design features continue to plunge deeper into the submicron regime, as in fabricating devices having a design rule of about 0.12 micron and under. The accurate formation of ultra-shallow junction depths (Xj) having high reliability in an efficient manner poses a particularly challenging problem.
Preamorphization techniques, as by ion implanting silicon (Si) or germanium (Ge), to define the contours of source/drain regions prior to dopant implantation and annealing have been employed to reduce the channeling effect and reduce transient enhanced diffusion (TED), and to reduce the activation temperature. Such preamorphization (SPE) techniques, however, are not without disadvantageous consequences. For example, implanted Si and Ge ions tend to migrate beyond the intended source/drain regions resulting in what is referred to as implantation straggle, both vertically and horizontally, making it extremely difficult to precisely define ultra-shallow source/drain extensions, e.g., below 400 xc3x85.
As the design rules plunge into the deep sub-micron range, the channel length, i.e., distance between junctions across the channel, evolves as a critical dimension, particularly as the channel length is reduced to about 1,000 xc3x85 and under. Natural variations in junction position as well as variations arising from processing render it difficult to accurately design devices. Alteration of a doping profile from TED as well as implantation straggle exacerbate design problems.
Conventional silicon-on-insulator (SOI) types of substrates have evolved and basically comprise a substrate, a buried oxide layer thereon, and a semiconductor layer on the buried oxide layer which constitutes the xe2x80x9cbodyxe2x80x9d of the transistor. In such SOI devices, the body floats in that there is no direct electrical connection to it. As the source and drain regions are isolated from the substrate, junction capacitance is reduced, i.e., when an electrical signal changes on either or both source and drain, there is significantly less capacitive coupling to the substrate. As electrical isolation is facilitated employing an SOI substrate, certain electrical elements of the circuit can be positioned closer together, thereby reducing the die size. SOI structures also offer the advantage of more rapid switching. In addition, latchup, which typically occurs in standard CMOS devices, does not exist employing SOI substrates, since the substrate is isolated by the buried oxide. Static or plasma arcing is also reduced in SOI devices.
There are, however, disadvantages attendant upon employing SOI substrates in fabricating semiconductor devices. A notable disadvantage is what is referred to as xe2x80x9cfloating body effectsxe2x80x9d. For example, it takes a considerable period of time for an ejected charge to leak out. As a result, transient bipolar effects can occur wherein a parasitic bipolar transistor turns on parallel to the MOSFET. In addition, hysteresis effects occur.
There exists a need for efficient methodology enabling the fabrication of semiconductor devices having accurate ultra-shallow junctions. There exists a particular need for efficient methodology enabling the fabrication of semiconductor devices having accurate ultra-shallow junctions based upon SOI substrates without floating body effects.
An advantage of the present invention is a method of manufacturing a semiconductor device having an SOI structure with reduced floating body effects.
Additional advantages and other features of the present invention will be set forth in the description which follows and, in part, will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device, the method comprising: forming a silicon-on-insulator (SOI) structure comprising: a lower silicon substrate; a buried insulating layer on the substrate; and an upper layer of crystalline silicon on the insulating layer; forming a gate electrode, having an upper surface and side surfaces, on the upper silicon layer with a gate dielectric layer therebetween; ion implanting dopant impurities to form source extensions and source regions in the upper silicon layer on a source-side thereof and to form drain extensions and drain regions in the upper silicon layer on a drain-side thereof; implanting ions into the source-side of the upper silicon layer to form a buried amorphous region therein while masking the drain-side of the upper silicon layer; and recrystallizing the buried amorphous region leaving source-side stacking faults.
Embodiments of the present invention comprise forming an SOI structure with a silicon oxide buried insulating layer, ion implanting Xe or a heavier ion at an implantation dosage of about 80xc3x971013 to about 1.2xc3x971014 ions/cm2 and an implantation energy of about 70 KeV to about 150 KeV, to form the buried amorphous region extending from below the upper surface of the upper silicon layer across about 50% to about 80%, e.g., about 80%, of the upper silicon layer. A metal, such as cobalt (Co) is then deposited and silicidation implemented, as at first and second stages, with a second stage at a temperature of about 700xc2x0 C. to about 800xc2x0 C. to form cobalt silicide layers. During such silicidation annealing, the buried amorphous region is crystallized leaving the source-side stacking faults and the source/drain implants are activated.
Additional advantages of the present invention will become readily apparent to those skilled in the art from the following detailed description, wherein embodiments of the present invention are described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.